1. Technical Field
The present invention relates to thick silicon, backside thinned, image sensors.
2. Related Art
As the size of the image sensors in individual pixels that are part of a sensing array become increasingly smaller, various designs attempt to more efficiently capture the incident light that illuminates the sensing array. One approach that can be used is to collect light from the “backside” of (e.g., underneath) the CMOS image sensor. Using the backside of the image sensor allows photons to be collected in an area that is relatively unobstructed by the many dielectric and metal layers that are normally used to form a typical image sensor. A backside illuminated (BSI) image sensor can be made by thinning the silicon substrate of the image sensor, which reduces the amount of silicon through which incident light traverses before the sensing region of the image sensor is encountered.
Backside-thinned, thick, silicon imagers are typically used in scientific and military applications where the additional sensitivity and performance associated with backside processing justifies the additional processing expense. The two primary advantages of backside processing in conjunction with thick silicon absorber layers are high effective open area ratio even when used with low F# optics and improved absorption of light in the near infra red region of the spectrum (˜700-1100 nm). The term thick silicon for the purpose of this discussion is defined as a silicon thickness that exceeds ˜½ times the dimension of the pixel pitch and is in excess of ˜5 microns of total thickness. When the silicon thickness exceeds the pixel pitch, significant photo-carrier diffusion into adjacent pixels can occur. This carrier diffusion is a well understood trade-off that can be mitigated in a variety of ways. A particularly good discussion of the issue including modeling, data and an alternate method of mitigation is found in US Patent application 2011/0024810 by Janesick. Patent application US 2011/0024810 is therefore incorporated by reference into the present disclosure. Janesick addresses the problem of carrier diffusion via the application of an electric field to a low-doped silicon layer in which the bulk of the near infra-red (NIR) photons (or other photons) are absorbed. Janesick generates the electric field via the application of a bias voltage on the back surface of the backside thinned image sensor. The bias voltage required to generate the photo-carrier drift field is applied to a “Mono-Layer of Metal” deposited on the back surface of the sensor. The applied electric field causes the photo-generated carriers to drift into the proximate charge collection node with minimal cross-diffusion onto adjacent pixels.
Application of a drift field in turn minimizes the charge diffusion associated degradation of image quality. The sharpness of the image generated by silicon CMOS or CCD sensors can be quantified by measuring a sensors modulation transfer function or MTF. MTF is degraded in the absence of an electric field produced via the application of an external bias voltage as disclosed in Patent application US 2011/0024810 or via the incorporation of a doping ramp as shown in FIG. 8 of U.S. Pat. No. 7,005,637 by Costello et al. Although these techniques minimize the MTF degradation associated with photo-carrier diffusion, they do not address optical cross-talk effects that are present in thick silicon detectors particularly when illuminated with low F# optics. When backside thinned silicon image sensors are illuminated with low F# optics the cone of light representing the incoming photons subtends a significant angle; for example a F#=1 simple lens will result in an extreme ray half angle of 45 degrees off the ray normal to the image sensor surface. Although the ray will approach normal as described by Snell's law of refraction, the ray will still retain a significant transverse component with respect to a normal ray. Consequently, there is still a significant mixing of adjacent pixel signals in thick silicon sensors that is not addressed by the incorporation of a drift field. Similarly, un-absorbed light that reaches the front surface of the backside-thinned sensor can reflect off of various interfaces and metal layers at high angles and thereby be absorbed in the silicon underlying adjacent pixels. These optical effects represent an additional undesired MTF degradation mechanism.
It should be noted that the optical cross-talk MTF degradation mechanisms are somewhat dependant on the F# of the incoming light. Consequently, when used in a system that employs an auto-iris lens, the pixel cross talk will change as a function of the lens F# which will in turn vary with scene illumination. While this may be a minor issue for monochrome systems, it complicates the signal processing required for color cameras particularly for extended color space applications that include a NIR channel.
Other isolation techniques applied to backside thinned CMOS imagers include the use of deep trench isolation as detailed by Venezia et al. in U.S. Pat. No. 7,800,192. The deep trench provides both a degree of optical isolation between pixels as well as complete separation of the silicon in which the photoelectrons diffuse. Venzia references multiple embodiments of the deep trench isolated pixel. Most embodiments incorporate a trench that is formed during the standard front-side processing of the device and include a p-well surrounding the trench. The formation of this p-well serves to “passivate” the trench walls, lowering surface generated dark current and the recombination rate of photoelectrons at the trench edge. Passivation of the walls of the trench are critical to the performance of the image sensor. This passivation is easily accomplished during front-side wafer processing via implant and anneal or spin-on-glass diffusion. Deep trench passivation via implant or spin on glass require high temperature processing that cannot be performed after the silicides and metal interconnect lines have been generated. Consequently, these passivation approaches are only applicable to front-side generated deep trenches. Trenches generated from the backside of the sensor must rely on alternate passivation techniques. In FIG. 7 of U.S. Pat. No. 7,800,192 Venzia shows the use of a passivation layer labeled as 740 and described as a p-type implant for passivation. Flat backside surfaces can be implanted and annealed by means such as a short duration laser pulse in order to activate the implant. This pulse-anneal approach allows the thermal budget of a finished CMOS sensor to be met while simultaneously achieving a high quality back surface passivation. Unfortunately, pulse anneal approaches do not work well on deep trenches formed on the backside finished CMOS devices. The pulse power required to activate the p-type dopant deep within the trench exceeds the thermal budget of the sensor.
Venzia does not teach an approach to passivate deep trenches generated on the backside of finished CMOS image sensors. Investigations at Intevac have shown that failure to passivate the vertical surfaces of trenches where the trench surface is more proximate to the photoelectron generation point than the depletion edge of the CMOS imager sense node will result in severe signal loss thereby negating the benefit associated with backside thinning the sensor. Although U.S. Pat. No. 7,800,192 does not call out specific silicon thickness, beyond the 1 to 3 micron thickness callout in FIG. 3, or pixel pitch limits, based on the embodiments that employ the generation of backside deep trenches, the performance of a backside trench approach lacking wall passivation places practical limits on the dimensions over which Venzia's teachings are functional. Specifically, in cases where the un-passivated backside trench depth exceeds the pixel pitch, performance of a backside thinned sensor will be significantly degraded. Similarly, it should be noted that if the depletion region surrounding the sense node of the CMOS imager intersects the unpassivated backside trench, the dark noise of the sensor will be significantly increased. The described shortcomings, signal loss and increased dark current, are significant and the resulting poor sensor performance would disqualify this approach for most commercial and military applications.
The limitations of previously described approaches are best understood when viewed in terms of the design choices that result from the performance requirements of scientific and night vision applications. One common requirement is to simultaneously meet low dark noise, high sensor MTF values and achieve high sensitivity to wavelengths of light ranging from the near ultra-violet (UV) range to NIR light. Scientific sensors may be required to measure light spectra from ˜200 nm to ˜1.06 micron wavelength. Similarly, military sensors may be required to have color daylight response and high sensitivity to the light available on a moonless star-lit night. In either case, the absorption coefficient of silicon is sufficiently low as to require silicon thickness in excess of 3 microns. More demanding applications may require silicon absorption thicknesses in excess of 50 microns without sacrificing good collection efficiency of the photoelectrons generated near the back surface of the sensor. Typical scientific imager pixel pitches range from the ˜5 through ˜25 microns. If we take as a basis the example of a scientific sensor with 10 micron pixel pitch and a 30 micron silicon thickness, there would be a ˜3:1 aspect ratio of pixel pitch to silicon back surface to sense node distance. If this scientific sensor was fabricated by the approach described by US Patent application 2011/0024810 by Janesick, the sensor would show good response and low dark current but the MTF of the sensor would show significant degradation when illuminated with low F number optics as a result of NIR light optical cross talk. On the other hand, if the sensor were fabricated as described by U.S. Pat. No. 7,800,192, Venzia, with unpassivated deep trenches generated from the back surface of the sensor, MTF would be good but very little visible light signal, generated near the back surface of the sensor, would be collected by the sense node located near the front surface of the sensor.
Recently Al2O3 has also been investigated as a “surface passivation” approach for crystalline silicon solar cells. It should be noted that for solar cells, surface passivation generally refers simply to surface treatments that enhance cell quantum efficiency over a range of illumination levels consistent with dawn to full sun daylight intensities. Low dark current injection is not typically a solar cell requirement. In stark contrast to the solar cell application, scientific image sensors are required to perform well even in the darkest of conditions. Ideally, the surface passivation of a back thinned scientific image sensor should not result in a significant increase in dark current over the thermal generation limit for the sensors silicon optical absorption layer. Similarly, the recombination rate at the passivated surface should be low compared to the lowest anticipated detectable light level. For sensors used in night vision or scientific microscope applications, detection of light levels that result in a single photoelectron per pixel per frame may be required. Consequently, “passivation” processes that apply to solar cells, though similarities exist, are not necessarily sufficient for application to backside thinned silicon image sensors.
Disclosed embodiments provide a back-thinned silicon image sensor having a passivated back surface. The back surface may include deep trench which are also passivated. According to one aspect, the trenches have a cross section in the shape of long “neck” section leading to an expanded bottom, somewhat like a cross section of a wine decanter. This shape of the trenches forms a choke or funnel for the photoelectrons traveling through the backside silicon towards the photosensitive part of the sensor. A color filter is adhered to the backside. The color filter may include RGB and NIR pixels. The sensor can be used in an EBAPS photosensor. The passivation layer may be Al2O3, or a combined Al2O3 layer over a layer of highly doped silicon in the back-thinned silicon image sensor.
Disclosed aspects also provide a back-thinned silicon image sensor passivated with a conformal, low thermal budget passivation layer and incorporating backside etched deep trench geometry to provide pixel level isolation. The sensor may be used in an EBAPS device. A color sensor may be adhered to the passivated backside. The color sensor may include RGB and NIR pixel filters. The conformal passivation may be provided over a highly doped surface of the back-thinned silicon image sensor.